View ADXL313_6384640.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3 - axis, 0.5 g /1 g /2 g /4 g digital accelerometer data sheet ADXL313 rev. 0 document feedback infor mation furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specificati ons subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9 106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features ultra low power (scales automatically with data rate) as low as 30 a in measurement mode (v s = 3.3 v) as low as 0.1 a in standby mode ( v s = 3.3 v) low noise performance 1 50 g /hz typical for x - and y - axes 250 g /hz typical for the z - axis embedd ed, patent pending fifo technology minimizes host processor load user - selectable resolution fixed 10 - bit resolution for any g range fixed 1024 lsb/ g sensitivity for any g range resolution scales from 10 - bit at 0.5 g to 13 - bit at 4 g built - in motion detec tion functions for a ctivity/ i nactivity monitoring supply and i/o voltage range: 2.0 v to 3.6 v spi (3 - wire and 4 - wire) and i 2 c digital interfaces flexible interrupt modes mapp able to two interrupt pin s measurement range selectable via serial command bandwi dth selectable via serial command wide temperature range ( ? 40 c to + 105 c) 10,000 g shock survival pb free/rohs compliant small and thin: 5 mm 5 mm 1.45 mm lfcsp package qualified for automotive applications applications car a larm s hill s tart a id (hsa) systems electronic p arking b rake s data r ecorder s (black box es) general description the ADXL313 is a small, thin, low power, 3 - axis accelerometer with high resolution (13 - bit) measurement up to 4 g . digital output data is formatted as 16 - bit twos complement and is accessible through either a serial port interface ( spi ) (3 - wire or 4 - wire) or i 2 c digital interface. the ADXL313 is well suited for car alarm or black box applications. it measures the static acceleration of gravity in tilt - sensing applica - tions, as well as dynamic acceleration resulting from motion or shock. its high resolution ( 1024 lsb/ g ) and low noise (150 g /hz) enabl e resolution of inclination changes of as little as 0. 1 . a built - in fifo facilitates using oversampling techniques to improve resolution to as little as 0.0 25 of inclination. several built - in sensing functions are provided. activity and inactivity sensi ng detect s the presence or absence of motion and whether the acceleration on any axis exceeds a user - set level. these functions can be mapped to interrupt output pins. an integrated 32 - level fifo can be used to store data to minimize host processor interve ntion , resulting in reduced system power consumption . low power modes enable intelligent motion - based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. the ADXL313 is supplied in a small, thin 5 mm 5 mm 1.45 mm, 32 - lead lfcsp package and is pin compatible with the adxl312 accelerometer device. functional block dia gram figure 1 . 3-axis sensor sense electronics digi t al fi l ter ADXL313 power management contro l and interrupt logic seria l i/o int1 v s v dd i/o int2 sda/sdi/sdio sdo/a l t address scl/sclk gnd adc 32-leve l fifo cs 1 1469-001
ADXL313 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ........................................................................ 8 power sequencing ........................................................................ 8 power savings ............................................................................... 8 serial communications ................................................................. 10 spi ................................................................................................. 10 i 2 c ................................................................................................. 13 interrupts ..................................................................................... 15 fifo ............................................................................................. 15 self test ........................................................................................ 16 register map ................................................................................... 17 register definitions ................................................................... 18 applications information .............................................................. 22 power supply decoupling ......................................................... 22 mechanical considerations for mounting .............................. 22 threshold .................................................................................... 22 link mode ................................................................................... 22 sleep mode vs. low power mode ............................................. 22 using self test ............................................................................. 23 3200 hz and 1600 hz odr data formatting ........................ 24 axes of acceleration sensitivity ............................................... 25 solder profile ................................................................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 28 automotive products ................................................................. 28 revision history 4/1 3 revision 0 : initial version
data sheet ADXL313 rev. 0 | page 3 of 28 specifications t a = ? 40c to + 105c , v s = v dd i/o = 3.3 v, a cceleration = 0 g , unless otherwise noted. table 1. parameter 1 test conditions /comments min typ max unit sensor input each axis measur ement range user s electable 0.5 , 1 , 2 , 4 g nonlinearity percentage of full scale 0.5 % micro - nonlinearity measured over any 50 m g interval 2 % inter a xis alignment error 0.1 degrees cross - axis sensitivity 2 1 % output resolution eac h axis all g ranges default r esolution 10 bits 0.5 g r ange full r esolution e nabled 10 bits 1 g r ange full resolution e nabled 11 bits 2 g r ange full resolution e nabled 12 bits 4 g r ange full resolution e nabled 13 bits sensitivity ea ch axis sensitivity at x out , y out , z out any g - range, full resolution mode 1024 lsb/ g 0.5 g , 10 - bit or full resolution 921 1024 1126 lsb/ g 1 g , 10 - bit resolution 460 512 563 lsb/ g 2 g , 10 - bit resolution 230 256 282 lsb/ g 4 g , 10 - bit resol ution 115 128 141 lsb/ g sensitivity change due to temperature 0.01 %/c 0 g bias level each axis initial 0 g output t = 25c, x out , y out 50 m g t = 25c, z out 75 m g 0 g output drift over temperature ?40c < t < + 105c, x out , y out , referenced to initial 0 g output ?125 +125 m g ?40c < t < + 105c, z out , referenced to initial 0 g output ?200 +200 m g 0 g offset tempco x out , y out 0.5 m g /c z out 0.75 m g /c noise performance noise density x- , y - axes 150 g /hz z - axis 250 g /hz rms noise x- , y - axes , 100 h z output data rate ( odr) 1.5 m g rms z - axi s, 100 h z odr 2.5 m g rms output data rate/bandwidth user selectable measurement rate 3 6.25 3200 hz self test 4 data rate 10 0 hz, 2.0 v v s 3.6 v output change in x - axis 0.20 2.36 g output change in y - axis ?2.36 ?0.20 g output change in z - axis 0.30 3.70 g power supply operating voltage range (v s ) 2.0 3.6 v interface voltage range (v dd i/o ) 1.7 v s v supply current data rate > 100 hz 100 170 300 a data rate < 10 hz 30 55 110 a standby mode leakage current 0.1 2 a turn - on (wak e - up) time 5 1.4 ms temperature operating temperature range ?40 +105 c 1 all minimum and maximum specifications are guaranteed. typical specifications are not guaranteed . 2 cross - axis sensitivity is defined as coupling between any two axes . 3 bandwidth is half the output data r ate. 4 self test change is defined as the output ( g ) when the self_test bit = 1 ( in the data_format register , address 0x31 ) minus the output ( g ) when the self_test bit = 0 ( in the data_format register). due to device filtering, the output reaches its final value after 4 when enabling or disabling self test , where = 1/(data rate). 5 turn - on and wake - up times are determined by the user - defined bandwidth. at a 100 hz data rate, the turn - on and wake - up times are each approximately 11.1 ms. for other data rates, the turn - on and wake - up times are each approximately + 1.1 in milliseconds, where = 1/(data rate).
ADXL313 data sheet rev. 0 | page 4 of 28 absolute maximum rat ings table 2. parameter rating acceleration any axis, unpowered 10,000 g any axis, powered 10,000 g v s ?0.3 v to + 3.9 v v dd i/o ?0.3 v to + 3.9 v all other pins ?0.3 v to v dd i/o + 0.3 v or 3.9 v, whichever is less output short - circuit duration (any pin to ground) indefinite temperature range powered ? 40 c to + 125 c storage ? 40 c to + 125 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional o peration of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resist ance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja jc unit 32- lead lfcsp p ackage 27.27 30 c/w esd caution
data sheet ADXL313 rev. 0 | page 5 of 28 pin configuration an d function descripti ons figure 2 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 gnd this pin m ust be connected to ground . 2 reserved res erved. this pin must be connected to v s or left open . 3 gnd this pin m ust be connected to ground . 4 gnd this pin m ust be connected to ground . 5 v s supply voltage . 6 cs chip select. 7 reserved reserved. this pin m ust be left open . 8 to 19 nc no connect . do not connect to this pin. 20 int 1 interrupt 1 output . 21 int 2 interrupt 2 output . 22 reserved reserved . this pin m ust be connected to gnd or left open . 23 sdo/alt address serial data out put/ alternate i 2 c address select . 24 sda/sdi/sdio serial data (i 2 c)/serial data in put (spi 4 - wire)/ serial data in put /out put (spi 3 - wire) . 25 nc no connect . do not connect to this pin. 26 scl/sclk i 2 c serial communications clock /spi serial communications clock . 27 to 30 nc no connect . do no t connect to this pin. 31 v dd i/o digital interface supply voltage . 32 nc no connect . do not connect to this pin. ep exposed pad. the exposed pad must be soldered to the ground plane. notes 1. nc = no connec t . do not connect t o this pin. 2. the exposed p ad must be soldered t o the ground plane. 24 sda/sdi/sdio 23 sdo/a l t address 22 rese r ved 21 int2 20 int1 19 nc 18 nc 17 nc 1 2 3 4 5 6 7 8 gnd rese r ved gnd gnd v s cs rese r ved nc 9 10 1 1 12 13 14 15 16 nc nc nc nc nc nc nc nc 32 31 30 29 28 27 26 25 nc v dd i/o nc nc nc nc scl/sclk nc t op view (not to scale) ADXL313 1 1469-002
ADXL313 data sheet rev. 0 | page 6 of 28 typical performance characteristics figure 3 . x - axis acceleration vs. temperature , three lots (n = 80) figure 4 . y - axis acceleration vs. temperature , three lots (n = 80) figure 5 . z - axis acceleration vs. temperature , three lots (n = 8 0) figure 6 . x - axis nonlinearity , 2 g input range figure 7 . y - axis nonlinearity , 2 g input range figure 8 . z - axis nonlinearity , 2 g input range ?125 ?100 ?75 ?50 ?25 0 25 50 75 100 125 10 30 50 70 90 1 10 acceler a tion ( g) temper a ture (c) 1 1469-003 ?50 ?30 ?10 ?125 ?100 ?75 ?50 ?25 0 25 50 75 100 125 ?50 ?30 ?10 10 30 50 70 90 1 10 acceler a tion ( g) temper a ture (c) 1 1469-004 ?200 ?150 ?100 ?50 0 50 100 150 200 10 30 50 70 90 1 10 acceler a tion ( g) temper a ture (c) 1 1469-005 ?50 ?30 ?10 ?1.0 ?0.5 0 0.5 1.0 ?40 ?30 ?20 ?10 0 10 20 30 40 0 500 1000 1500 2000 nonlinearit y (%fs) nonlinearit y (m g) input acceler a tion (m g) 1 1469-006 ?2000 ?1500 ?1000 ?500 ?1.0 ?0.5 0 0.5 1.0 ?40 ?30 ?20 ?10 0 10 20 30 40 ?2000 ?1500 ?1000 ?500 0 500 1000 1500 2000 nonlinearit y (%fs) nonlinearit y (m g) input acceler a tion (m g) 1 1469-007 ?1.0 ?0.5 0 0.5 1.0 ?40 ?30 ?20 ?10 0 10 20 30 40 0 500 1000 1500 2000 nonlinearit y (%fs) nonlinearit y (m g) input acceler a tion (m g) 1 1469-008 ?2000 ?1500 ?1000 ?500
data sheet ADXL313 rev. 0 | page 7 of 28 figure 9 . x - axis microlinearity , 50 m g step size figure 10 . y - axis microlinearity , 50 m g step size figure 11 . z - axis microlinearity , 50 m g step size figure 12 . standby mode current consumption , v s = v dd i/o = 3.3 v , 25c figure 13 . current consumption, measurement mode, data rate = 100 hz , v s = v dd i/o = 3.3 v , 25c figure 14 . supply current vs. supply v oltage, v s at 25c ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?1000 ?750 ?500 ?250 0 250 500 750 1000 microlinearit y (%) input acceler a tion (m g ) 1 1469-009 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?1000 ?750 ?500 ?250 0 250 500 750 1000 microlinearit y (%) input acceler a tion (m g ) 1 1469-010 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?1000 ?750 ?500 ?250 0 250 500 750 1000 microlinearit y (%) input acceler a tion (m g ) 1 1469-0 1 1 0 10 20 40 30 50 80 70 60 30 50 70 90 1 10 130 150 170 190 210 230 250 270 290 310 current (na) percent of popul a tion (%) 1 1469- 1 18 0 5 10 20 15 25 35 30 100 120 140 160 180 200 220 240 260 280 300 current consumption (a) percent of popul a tion (%) 1 1469- 1 19 0 50 100 150 200 2.0 2.4 2.8 3.2 3.6 supp l y vo lt age (v) supp l y current (a) 1 1469-233
ADXL313 data sheet rev. 0 | page 8 of 28 theory of operation the ADXL313 is a complete 3 - axis acceleration measurement system with a selectable measurement range of 0.5 g, 1 g, 2 g, or 4 g . it measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity, which allows it to be used as a tilt sensor. the sensor is a polysilicon surface - micromachined structure built on top of a silicon wafer. polysilicon springs sus pend the structure over the surface of the wafer and provide a resistance against acceleration forces. deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. a cceleration deflects the beam and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. phase - sensitive demodulation is used to determine the magnitude and polarity of the acceleration. power s equencing power can be applied to v s or v dd i/o in any sequence without damaging the ADXL313 . all possible power - on modes are summarized in table 5 . the interface voltage level is set with the interface supply voltage, v dd i/o , which must be present to ensure that the ADXL313 does not create a conflict on the communication bus. for single - suppl y operation, v dd i/o can be the same as the main supply, v s . in a dual - supply application, however, v dd i/o can differ from v s to accommodate the desired interface voltage , as long as v s is greater than or equal to v dd i/o . after v s is applied, the device enters standby mode, where power consumption is minimized and the device waits for v dd i/o to be applied and for the command to enter measurement mode to be received. (this command can be initiated by setting the measure bit in the power_ctl register (add ress 0x2d).) in addition, any register can be written to or read from to configure the part while the device is in standby mode. it is recommended that the device be configured in standby mode before measurement mode is enabled . clearing the measure bit re turns the device to the standby mode. power saving s power modes the ADXL313 automatically modulates its power consumption in proportion to its output data rate, as outlined in table 5 . if additional power savings are desired, a lower power mode is available. in this mode, the internal sampling rate is reduced, allowing for power savings in the 12.5 hz to 400 hz data rate range at the expense of sli ghtly greater noise. to enter low power mode, set the low_power bit (bit 4) in the bw_rate register (address 0x2c). the current consumption in low power mode is shown in table 6 for cases where there is an adva ntage to using low power mode. use of low power mode for a data rate not shown in table 6 does not provide any advantage over the same data rate in normal power mode. therefore, it is recommended that only data rates shown in table 6 be used in low power mode. the current consumption values shown in table 5 and table 6 are for a v s of 3.3 v. table 5 . current consumption vs. data rate (t a = 25c, v s = v dd i/o = 3.3 v) output data rate (hz) bandwidth (hz) rate code i dd (a) 3200 1600 1111 170 1600 800 1110 115 800 400 1101 170 400 200 1100 170 200 100 1011 170 100 50 1010 170 50 25 1001 115 25 12.5 1000 82 12.5 6.25 0111 65 6.25 3.125 0110 57 table 6. current consumption vs. data rate, low power mode (t a = 25c, v s = v dd i/o = 3.3 v) output data rate (hz) bandwidth (hz) rate code i dd (a) 400 200 1100 115 200 100 1011 82 100 50 1010 65 50 25 1001 57 25 12.5 1000 50 12.5 6.25 0111 43 table 7 . power sequencing condition v s v dd i/o description power off off off the device is completely off, but there is a potential for a communication bus conflict. bus disabled on off the device is on in standby mode, but communication is unavailable, and the device creates a conflict on the communication bus. minimize the duration of this state during power - up to prevent a conflict. bus enabled off on no functions are available, but the device does not create a conflict on the communication bus. standby or measurement on on the device is in standby mode, awaiting a command to enter measurement mode, and al l sensor functions are off. after the device is instructed to enter measurement mode, all sensor functions are available.
data sheet ADXL313 rev. 0 | page 9 of 28 autos leep mode additional power savings can be obtained by having the ADXL313 automatically switch to sleep mode during periods of inactivity. to enable this feature , set the thresh_inact register (address 0x25) to an acceleration threshold value . levels of acceleration below this threshold are re garded as no activity. set time_inact (address 0x26) to an appropriate inactivity time period . then set the auto_sleep bit and the link bit in the power_ctl register (address 0x2d) . if the device does not detect a level of acceleration in excess of thres h _inact for time_inact secon ds, the device is transitione d to sleep mode automatically. current consumption at less than 10 hz data rates used in this mode is typically 55 a for a v s of 3.3 v. standby mode for even lower power operation , standby mode can be used. in standby mode , current consumption is reduced to 0.1 a (typical). in this mode , no m easurements are made. standby m ode is entere d by clearing the measure bit (b it 3) in the power_ctl register (address 0 x2d). placing the device into s tandby m ode preserve s the contents of the fifo.
ADXL313 data sheet rev. 0 | page 10 of 28 serial communication s i 2 c and spi digital communications are available. in both cases, the ADXL313 operates as a slave. i 2 c mode is enabled if the cs pin is tied high to v dd i/o . the cs pin must always be tied high to v dd i/o or be driven by an external controller because there is no default mode if the cs pin is left unconnected. therefore, not taking these prec autions may result in an inability to communicate with the part. in spi mode, the cs pin is controlled by the bus master. in both spi and i 2 c modes of operation, ignore data transmitted from the ADXL313 to the master device during writes to the ADXL313 . spi for spi communication , either 3 - or 4 - wire configuration is possible, as shown in the connection diagrams in figure 15 and figure 16. clearing the spi bit in the data_format register (address 0x31) selects 4 - wire mode, whereas setting the spi bit selects 3 - wire mode. the maximum spi clock speed is 5 mhz with 100 pf maximum loading, and the timing scheme follows clock polarity (cpol) = 1 and clock phase (cpha) = 1. if power is applied to the ADXL313 before the clock pola rity and phase of the host processor are configured, the cs pin must be brought high before changing the clock polarity and phase. when using the 3 - wire spi configuration , it is recommended that the sdo pin be either pulled up to v dd i/o or pulled down to gnd via a 10 k? resistor. figure 15 . 3 - wire spi connection diagram figure 16 . 4 - wire spi connection diagram cs is the serial port enable line and is controll ed by the spi master. this line must go low at the start of a transmission and high at the end of a transmission, as shown in figure 17 to figure 19. sclk is the serial por t clock and is supplied by the spi master. sclk idle s high during a period of no transmission. sdi and sdo are the serial data input and output, respectively. data is updated on the falling edge of sclk and sampled on the rising edge of sclk. to read or wr ite multiple bytes in a single transmission, the multiple - byte bit, located after the r/ w bit in the first byte transfer (mb in figure 17 to figure 19 ), must be set. after the register addressing and the first byte of data, each subsequent set of clock pulses (eight clock pulses) causes the ADXL313 to point to the next register for a read or write. this shifting continues until the clock pulses cease and cs is deasserted. to perform reads or writes on different, nonsequential registers, cs must be deasserted between transmissions , and the new registe r must be addressed separately. the timing diagram for 3 - wire spi reads or writes is shown in figure 17 . the 4 - wire equivalents for spi reads and writes are shown in figure 18 and figure 19 , respectively. for correct operation of the part, the logic thresholds and timing parameters in table 8 and table 9 must be met at all times. use of the 3200 hz and 1600 hz output data rates is recommended only with spi communication rates greater than or equal to 2 mhz. the 800 hz output data rate is recommended only for communication speeds greater than or equ al to 400 khz, and the remaining data rates scale proportionally. for example, the minimum recommended communication speed for a 200 hz output data rate is 100 khz. operation at an output data rate below the recommended minimum may result in undesirable ef fects on the acceleration data, including missing samples or additional noise. processor d out d in/out d out ADXL313 cs sdio sdo sclk 1 1469-012 processor d out d out d in d out ADXL313 cs sdi sdio sclk 1 1469-013
data sheet ADXL313 rev. 0 | page 11 of 28 table 8 . spi digital input/output limit 1 parameter test conditions /comments min max unit digital input low level input voltage (v il ) 0.3 v dd i/o v high level input voltage (v ih ) 0.7 v dd i/o v low level input current (i il ) v in = v dd i/o 0.1 a high level input current (i ih ) v in = 0 v ? 0.1 a digital output low level output voltage (v ol ) i ol = 10 ma 0.2 v dd i/o v high le vel output voltage (v oh ) i oh = ?4 ma 0.8 v dd i/o v low level output current (i ol ) v ol = v ol, max 10 ma high level output current (i oh ) v oh = v oh, min ? 4 ma pin capacitance f in = 1 mhz, v in = 2.5 v 8 pf 1 limits ba sed on characterization results; not production tested. table 9 . spi timing (t a = 25c, v s = v dd i/o = 3.3 v ) 1 limit 2 , 3 parameter min max unit description f sclk 5 mhz spi clock frequency . t sclk 200 ns 1/(spi clock frequency) mark - space ratio for the sclk input is 40/60 to 60/40. t delay 5 ns cs fa lling edge to sclk falling edge . t quiet 5 ns sclk rising edge to cs rising edge . t dis 10 ns cs rising edge to sdo disabled . t cs ,dis 150 ns cs deassertion between s pi communications . t s 0.3 t sclk ns sclk low pulse width (space) . t m 0.3 t sclk ns sclk high pulse width (mark) . t setup 5 ns sdi valid before sclk rising edge . t hold 5 ns sdi valid after sclk rising edge . t sdo 40 ns sclk fal ling edge to sdo/sdio output transition . t r 4 20 ns sdo/sdio output high to output low transition . t f 4 20 ns sdo/sdio output low to output high transition . 1 the cs , sclk, sdi, and sdo pins are not internally pull ed up or down; they must be driven for proper operation. 2 limits based on characterization results, characterized with f sclk = 5 mhz and bus load capacitance of 100 pf; not production tested. 3 the timing values are measured corresponding to the input thr esholds (v il and v ih ) given in table 8 . 4 output rise and fall times measured with capacitive load of 150 pf.
ADXL313 data sheet rev. 0 | page 12 of 28 figure 17 . spi 3 - wire read/write figure 18 . spi 4 - wire read figure 19 . spi 4 - wire write cs t delay t setup t hold t sdo r/w mb a5 a0 d7 d0 address bits data bits t sclk t m t s t quiet sclk sdio sdo notes 1. t sdo is only present during reads. t r , t f t cs,dis 1 1469-014 cs x x x r mb a5 a0 d7 d0 x x x address bits data bits t dis sclk sdi sdo t quiet t sdo t setup t delay t sclk t m t s t r , t f t hold t cs,dis 1 1469-015 t delay t setup t hold t sdo t r , t f x x x w mb a5 a0 d7 d0 x x x address bits data bits t sclk t m t s t quiet t dis t cs,dis sclk sdi sdo cs 1 1469-016
data sheet ADXL313 rev. 0 | page 13 of 28 i 2 c with cs tied high to v dd i/o , the ADXL313 is in i 2 c mode, requiring a simple 2 - wire connection , as shown in figure 20. the ADXL313 conforms to the um10204 i 2 c - bus specificatio n and user manual , rev. 03 19 june 2007, available from nxp semiconductor. it supports standard (100 khz) and fast (400 khz) data transfer modes if the bus parameters given in table 10 and table 11 are met. single - or multiple - byte reads/writes are supported, as shown in figure 21 . with the alt address pin high, the 7 - bit i 2 c address for the device is 0x1d, followed by the r/ w bit. this translates to 0x3a for a write and 0x3b for a read. an alternate i 2 c address of 0x53 (followed by the r/ w bit) can be chosen by grounding the alt address pin (pin 23 ). this translates to 0xa6 for a wr ite and 0xa7 for a read. figure 20 . i 2 c connection diagram (address 0x53) if other devices are connected to the same i 2 c bus, the nominal operating voltage level of these other devices cannot exceed v dd i/o by more than 0.3 v. external pull - up resistors, r p , are necessary for proper i 2 c operation. to ensure proper operation, r efer to the um10204 i 2 c - bus specification and user manual , rev. 03 19 june 2007 , when selecting pull- up resistor values. table 10. i 2 c digital input/output limit 1 parameter test conditions /comments min max unit digital input low level input voltage (v il ) 0.3 v dd i/o v high level input voltage (v ih ) 0.7 v dd i/o v low level input current (i il ) v in = v dd i/o 0.1 a high level input current (i ih ) v in = 0 v ? 0.1 a digital output low level output voltage (v ol ) v dd i/o < 2 v, i ol = 3 ma 0.2 v dd i/o v v dd i/o 2 v, i ol = 3 ma 400 mv low level output current (i ol ) v ol = v ol, max 3 ma pin capacitance f in = 1 mhz, v in = 2.5 v 8 pf 1 limits based on characterization results; not production tested. figure 21 . i 2 c device addressing processor d in/out d out r p v dd i/o r p ADXL313 cs sda alt address scl 1 1469-017 notes 1. this start is either a restart or a stop followed by a start. 2. the shaded areas represent when the device is listening. 1 1469-133 master start slave address + write register address slave ack ack ack master start slave address + write register address slave ack ack ack ack master start slave address + write register address stop slave ack ack master start start 1 start 1 slave address + write register address nack stop slave ack ack data stop ack single-byte write multiple-byte write data data multiple-byte read slave address + read slave address + read ack data data data stop nack ack single-byte read
ADXL313 data sheet rev. 0 | page 14 of 28 table 11. i 2 c timing (t a = 25c, v s = v dd i/o = 3.3 v) limit 1 , 2 parameter min max unit description f scl 400 khz scl clock frequency t 1 2.5 s scl cycle time t 2 0.6 s scl high time t 3 1.3 s scl low time t 4 0.6 s start /repeated start condition hold time t 5 100 ns data setup time t 6 3 , 4 , 5 , 6 0 0.9 s data hold time t 7 0.6 s setup time for repeated start t 8 0.6 s stop condition setup time t 9 1.3 s bus - free time between a stop condition and a start condition t 10 300 ns rise time of both scl and sda when receiving 0 ns rise time of both scl and sda when receiving or transmitting t 11 250 ns fall tim e of sda when receiving 300 ns fall time of both scl and sda when transmitting 20 + 0.1 c b 7 ns fall time of both scl and sda when transmitting or receiving c b 400 pf capacitive load for each bus line 1 limits based on characterization results, with f scl = 400 khz and a 3 ma sink current; not production tested. 2 all values referred to the v ih and the v il levels given in table 10. 3 t 6 is the data hold time that is measured from the falling edge of scl. it applies to data in transmission and acknowledge. 4 a transmitting device must internally provide an output hold time of at least 300 ns for the sda signal (with respect to v ih , min of the scl signal) to bridge the undefined region of the falling edge of scl. 5 the maximum t 6 value must be met only if the device does not stretch the low period (t 3 ) of the scl signal. 6 the maximum value for t 6 is a function of the clock low time (t 3 ), the clock rise time (t 10 ), and the minimum data setup time (t 5(min) ). this value is calculat ed as t 6(max) = t 3 ? t 10 ? t 5(min) . 7 c b is the total capacitance of one bus line in picofarads. figure 22 . i 2 c timing diagram sda t 9 scl t 3 t 10 t 1 1 t 4 t 4 t 6 t 2 t 5 t 7 t 1 t 8 st art condition repe a ted st art condition st op condition 1 1469-018
data sheet ADXL313 rev. 0 | page 15 of 28 interrupts the ADXL313 provides two output pins for driving interrupts: int1 and int2. both interrupt pins are push - pull, low impedance pins with output specifications shown in table 12 . the default configuration of the interrupt pins is active high. this can be changed to active low by setting the int_invert bit in the data_format register (address 0x31) . all functions can be used simul taneously, with the only limiting feature being that some functions may need to share interrupt pins. interrupts are enabled by setting the appropriate bit in the int_enable register (address 0x2e) and are mapped to either the int1 or int2 pin based on th e contents of the int_map register (address 0x2f). when initially configuring the interrupt pins, it is recommended that the functions and interrupt mapping be completed before enabling the interrupts. when changing the con figuration of an interrupt, it i s recommended that the interrupt be disabled first, by clearing the bit corresponding to that function in the int_enable register, and then the function be reconfig - ured before enabling the interrupt again. configuration of the functions while the interrup ts are disabled helps to prevent the accidental generation of an interrupt. the interrupt functions are latched and cleared either by reading the data registers (address 0 x 32 to address 0 x 37 ) until the inter - rupt condition is no longer valid for the data - related interrupts or by reading the int_source register (address 0x30) for the remaining interrupts. th e following section s describe the interrupts that can be set in the int_enable register and monitored in the int_source register. data_ready the data_re ady bit is set when new data is available and is cleared when no new data is available. activity the activity bit is set when acceleration greater than the value stored in the thresh_act register (address 0x24) is sensed . inactivity the inactivity bit is s et when acceleration of less than the value stored in the thresh_inact register (address 0x25) is sensed for more time than is specified in the time_inact register (address 0x26). the maximum value for time_inact is 255 sec. watermark the watermark bit is set when the number of samples in the fifo equals the va lue stored in the samples bits in the fifo_ctl register ( address 0x38). the watermark bit is cleared automatically when the fifo is read, and the content returns to a value below the value stored in the samples bits. overrun the overrun bit is set when new data replaces unread data. the precise operation of the overrun function depends on the fifo mode. in bypass mode, the overrun bit is set when new data replaces unread data in the data _ x x , data _ y x , and data _ z x registers ( address 0x32 to address 0x37). in all other modes, the overrun bit is set when the fifo is filled. the overrun bit is automatically cleared when the contents of fifo are read. fifo the ADXL313 contains patent pending technology for an embedded memory management system with a 32 - level fifo that can be used to minimize host processor burden. this buffer has four modes: bypass, fifo, stream, and trigger (see table 17 ). each mode is selected by the settings of the fifo_mode bits in the fifo_ctl register (address 0 x 38 ). bypass mode in bypass mode, the fifo is not operational and, therefore, remains empty. table 12 . interrupt pin digital output limit 1 parameter test conditions /comments min max unit digital output low level output voltage (v ol ) i ol = 300 a 0.2 v dd i/o v high level output voltage (v oh ) i oh = ?150 a 0.8 v dd i/o v low level outp ut current (i ol ) v ol = v ol, max 300 a high level output current (i oh ) v oh = v oh, min ? 150 a pin capacitance f in = 1 mhz, v in = 2.5 v 8 pf rise/fall time rise time (t r ) 2 c load = 150 pf 210 ns fall time (t f ) 3 c load = 150 pf 150 ns 1 limits based on characterization results, not production tested. 2 rise time is measured as the transition time from v ol, max to v oh, min of the intx pin. 3 fall time is measured as the transition time from v oh, min to v ol, max of the intx pin.
ADXL313 data sheet rev. 0 | page 16 of 28 fifo mode in fifo mode, data from measurements of the x - , y - , and z - axes are stored in the fifo. when the number of samples in the fifo equals the level specified in the samples bits of the fifo_ctl register (address 0x38), the watermark interrupt is set. the f ifo continues accumulating samples until it is full (32 samples from measurements of the x - , y - , and z - axes) and then stops collecting data. after the fifo stops collecting data, the device continues to operate; therefore, features such as activity detecti on can be used after the fifo is full. the watermark interrupt contin - ues to occur until the number of samples in the fifo is less than the value stored in the samples bits of the fifo_ctl register. stream mode in stream mode, data from measurements of the x - , y - , and z - axes is stored in fifo. when the number of samples in the fifo equals the level specified in the samples bits of the fifo_ctl register (address 0x38), the watermark interrupt is set. fifo continues accumulating samples and holds the latest 3 2 samples from measurements of the x - , y - , and z - axes, discarding older data as new data arrives. the watermark interrupt continues occurring until the number of samples in fifo is less than the value stored in the samples bits of the fifo_ctl register. t rigger mode in trigger mode, the fifo accumulates samples, holding the latest 32 samples from measurements of the x - , y - , and z - axes. after a trigger event occurs and an interrupt is sent to the int1 or int2 pin (determined by the trigger bit in the fifo_c tl register), fifo keeps the last n samples (where n is the value specified by the samples bits in the fifo_ctl register) and then operates in fifo mode, collecting new samples only when the fifo is not full. a delay of at least 5 s must be present betwee n the trigger event occurring and the start of reading data from the fifo to allow the fifo to discard and retain the necessary samples. additional trigger events cannot be recognized until the trigger mode is reset. to reset the trigger mode, set the dev ice to bypass mode and then set the device back to trigger mode. note that the fifo data must be read first because placing the device into bypass mode clears fifo. retrieving data from fifo the fifo data is read through the data _ x x , data _ y x , and data _ z x r egisters (address 0x32 to address 0x37). when the fifo is in fifo, stream, or trigger mode, reads to the data _x x , data _x y, and data _ z x registers read data stored in the fifo. each time data is read from the fifo, the oldest x - , y - , and z - axes data is place d into the data _x x , data _y x, and data _ z x registers. if a single - byte read operation is performed, the remaining bytes of data for the current fifo sample are lost. therefore, all axes of interest must be read in a burst (or multiple - byte) read operation. to ensure that the fifo has completely popped (that is, that new data has completely moved into the data_xx, data_yx, and data_zx registers), there must be at least 5 s between the end of reading the data registers and the start of a new read of the fifo or a read of the fifo_status register (address 0x39) . the end of reading a data register is signified by the transition from register 0x37 to register 0x38 or by the cs pin going high. for spi operation at 1.6 mhz or less, the registe r addressing portion of the transmission is a sufficient delay to ensure that the fifo has completely popped. for spi operation greater than 1.6 mhz, it is necessary to deassert the cs pin to ensure a total delay of 5 s; otherwise, the delay is not sufficient. the total delay necessary for 5 mhz operation is at most 3.4 s. this is not a concern when using i 2 c mode because the communication rate is low enough to ensure a sufficient delay between fifo reads. self t est the ADXL313 incorporates a self test feature that effectively tests its mechanical and electronic systems simultaneously. when the self test function is enabled (via the self_test bit in the data_format register, address 0x31), an electrostatic force is exerted on the mechanical sensor. this electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the acceleration experienced by the device. this added electrostatic force results in an output change in the x - , y - , and z - axes. because the electrostatic force is proportional to v s 2 , the output change varies with v s . the self test feature of the ADXL313 also exhibits a bimodal behavior . however, the limits shown in table 1 and table 13 are valid for all potential self test values across the entire allowable voltage range. use of the self test feature at data rates of less than 100 hz or at 1600 hz may yield values outside these limits. therefore, the part must be in normal power operation (low_power bit = 0 in the bw_rate register, addres s 0x2c) and be placed into a data rate of 100 hz through 800 hz or 3200 hz for the self test function to operate correctly. table 13. self test output (t a = 25c, 2.0 v v s 3.6 v ) axis min ( g ) max ( g ) x 0.20 2.36 y ? 2.36 + 0.20 z 0.30 3.70
data sheet ADXL313 rev. 0 | page 17 of 28 register map table 14 . register map reg name type d7 d6 d5 d4 d3 d2 d1 d0 reset value 0x00 devid_0 r devid_0[7:0] 0xad 0x01 devid_1 r devid_1[7:0] 0x1d 0x02 partid r partid[7:0] 0xdc 0x03 revid r revid[7:0] 0x00 0x04 xid r xid[7:0] 0x00 0x05 to 0x17 reserved rsvd reserved 0x18 soft_reset r/ w soft_reset[7:0] 0x00 0x19 to 0x1d reserved rsvd reserved 0x1e ofsx r/ w ofsx[7:0] 0x00 0x1f ofsy r/ w ofsy[7:0] 0x00 0x20 ofsz r/ w ofsz[7:0] 0x00 0x21 to 0x23 reserved rsvd reserved 0x24 thresh_act r/ w thresh_act[7:0] 0x00 0x25 thresh_inact r / w thresh_inact[7:0] 0x00 0x26 time_inact r/ w time_inact[7:0] 0x00 0x27 act_inact_ctl r/ w act_ ac/dc act_x act_y act_z inact_ ac/dc inact_x inact_y inact_z 0x00 0x28 to 0x2b reserved rsvd reserved 0x2c bw_rate r/ w 0 0 0 low_power rate [3:0] 0x0a 0x2d power_ctl r/ w 0 i2c_ disable link auto_sleep measure sleep wake - up [1:0] 0x00 0x2e int_enable r/ w data_ ready 0 0 a ctivity i nactivity 0 watermark overrun 0x00 0x2f int_map r/ w data_ ready 0 0 activity inactivity 0 watermark overrun 0x00 0x30 int_source r data_ ready 0 0 activity inactivity 0 watermark overrun 0x02 0x31 data_format r/ w self_ test spi int_ invert 0 full_ res justify range [1:0] 0x00 0x32 data_ x0 r data_x0[7:0] 0x00 0x33 data_x1 r data_x1[7:0] 0x00 0x34 data_y0 r data_y0[7:0] 0x00 0x35 data_y1 r data_y1[7:0] 0x00 0x36 data_z0 r data_z0[7:0] 0x00 0x37 data_z1 r data _z1[7:0] 0x00 0x38 fifo_ctl r/ w fifo_mode[1:0] t rigger samples [4:0] 0x00 0x39 fifo_status r fifo_trig 0 entries 0x00
ADXL313 data sheet rev. 0 | page 18 of 28 register definitions register 0x00 devid _ 0 (read only) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 0 1 1 0 1 the devid _0 reg ister holds a fixed d evice id identifying analog devices , inc., as the device manufacturer. the default value of this register is 0x ad. register 0x01 devid _ 1 (read only) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 1 1 0 1 the devid _ 1 register holds a fixed d evice id that further enhances traceability of the ADXL313 . the default value of this register is 0 x 1 d. register 0x02 partid (read only) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 0 1 0 1 1 the partid register ide nti fies the device as an ADXL313 . the default hex adecimal value stored in this register, 0xdc, is meant to be interpreted as an octal value that corresponds to 313. if the user does not read bac k 0xdc from this register, assume that the device under test is not an ADXL313 device. register 0x0 3 rev id (read only) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 revid[7:0] the number contained in the revid reg ister represents the si licon revision of the ADXL313 . this number is incremented for any major silicon revision . register 0x0 4 x id (read only) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xid[ 7:0] the xid registe r stores a semi - unique serial number that is generated from the device trim and calibration process. register 0x 18 soft_reset (read/write) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 soft_reset[ 7:0 ] writing a value of 0x52 to register 0x 18 trigger s the soft reset function of the ADXL313 . the soft reset return s the ADXL313 to the beginning of its power - on initialization routine, clearing the configurati on settings that w ere written to the memory map, which allow s easy re configuration of the ADXL313 device. register 0x1e ofsx (read/write) , register 0x1f ofsy (read/write) , register 0x20 ofsz (r ead/write) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ofsx[ 7:0] ofsy[ 7:0] ofsz[ 7:0] the ofsx, ofsy, and ofsz registers are each eight bits and offer user - set offset adjustments in twos complement format with a scale factor of 3.9 m g /lsb (that is , 0x7f = 0.5 g ). the valu e stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. register 0x24 thresh_act (read/write) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 thresh_act[ 7:0 ] the thresh_act register is eig ht bits and holds the threshold value for detecting activity. the data format is unsigned ; therefore , the magnitude of the activity event is compared with the value in the thresh_act register . the scale factor is 15.625 m g /lsb. a value of 0 may result in u ndesirable behavior if the activity interrupt is enabled. register 0x25 thresh_inact (read/write) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 thresh_inact[ 7:0] the thresh_inact register is eight bits and holds the threshold value for detecting inactivity. the data format is unsigned ; therefore, the magnitude of the inactivity event is compared with the value in the thresh_inact register . the scale factor is 15.625 m g /lsb. a value of 0 may result in undesirable behavior if the inactivity interrupt is enabled. register 0x26 ti me_inact (read/write) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 time_inact[ 7:0 ] the time_inact register is eight bits and contains an unsigned time value. acceleration must be less than the value in the thresh_inact register for the amount of time represented by time_inac t for inactivity to be declared. the scale factor is 1 sec/lsb. unlike the other interrupt functions, which use unfiltered data (see the threshold section), the inactivity function uses filtered output data. at least one output sample must be generated for the inactivity interrupt to be triggered. this results in the function appearing unresponsive if the time_inact register is set to a value less than the time constant of the output data rate. a value of 0 resu lts in an interrupt when the output data is less than the value in the thresh_inact register . register 0x27 act_inact_ctl (read/write) d7 d6 d5 d4 act _ ac/dc act_x act_y act_z d3 d2 d1 d0 inact _ ac/dc inact_x inact_y inact_z act_ ac/dc and inact _ ac /dc bits a setting of 0 selects dc - coupled operation, and a setting of 1 enables ac - coupled operation. in dc - coupled operation, the current acceleration magnitude is compared directly with thresh_act and thresh_inact to determine whether activity or inacti vity is detected.
data sheet ADXL313 rev. 0 | page 19 of 28 in ac - coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. new samples of acceleration are then compared to this reference value and , if the magnitude of the d ifference exceeds the thresh_act value, the device triggers an activity interrupt. similarly, in ac - coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. a fter the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with thresh_inact . if the difference is less than the value in thresh_inact for the time in time_inact , the d evice is considered inactive and the inactivity interrupt is triggered. act_x and inact_x bits a setting of 1 enables x - , y - , or z - axis participation in detecting activity or inactivity. a setting of 0 excludes the selected axis from participation. if all axes are excluded, the function is disabled. for activity detection, all participating axes are logically ored, causing the activity function to trigger when any of the participating axes exceeds the threshold. for inactiv - ity detection, all participating axes are logically anded, causing the inactivity function to trigger only if all participating axes are below the threshold for the specified period of time. register 0x2c bw_rate (read/write) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 low_power rate low_power bit a setting of 0 in the low_power bit selects normal operation, and a setting of 1 selects reduced power operation, which has somewhat higher noise (see the power modes section for details). rate bits these bits sele ct the device bandwidth and output data rate (see table 5 and tabl e 6 for details). the default value is 0x0a, which translates to a 100 hz output data rate. select a n output data rate that is appropriate for the communication protocol and frequency selected. selecting too high of an output data rate with a low communication speed results in samples being discarded. register 0x2d power_ctl (read/write) d 7 d 6 d 5 d 4 0 i2c_ disable link auto_sleep d 3 d 2 d 1 d 0 measure sleep wake - up i2c_disable bit the ADXL313 is capable of communicating via spi or i 2 c transmission protocols. typically, these protocols do not overlap ; however , situations may arise where spi transactions can imitate an i 2 c start command. this cause s the ADXL313 to respond unexpectedly, caus ing a communications issue with other device s on the network. to ensure that the ADXL313 does not interpret spi commands as an i 2 c start condition, assert the i2c_disable bit. link bit a setting of 1 in the link bit with both the activit y and inactivity functions enabled delays the start of the activity function until inactivity is detected. after activity is detected, inactivity detection begins, preventing the detection of activity. this bit serially links the activity and inactivity fu nctions. when this bit is set to 0, the inactivity and activity functions are concurrent. additional information can be found in the link mode section. when clearing the link bit, it is recommended that the par t be placed into standby mode and then set back to measurement mode with a subsequent write. this is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleare d may have additional noise, especially if the device was asleep when the bit was cleared. auto_sleep bit if the link bit is set, a setting of 1 in the auto_sleep bit sets the ADXL313 to switch to sleep mode when inactivity is detected (that is, when acceleration is below the thresh_inact value for at least the time indicated by time_inact). a setting of 0 disables automatic switching to sleep mode. see the description of the sleep bit in the sleep bit section for more information. when clearing the auto_sleep bit, it is recommended that the part be placed into standby mode and then set back to measure - ment mode with a subsequent write. this is done to ens ure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the auto_sleep bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. measure bit a s etting of 0 in the measure bit places the part into standby mode, and a setting of 1 places the part into measurement mode. the ADXL313 powers up in standby mode with minimum power consumption. sleep bit a setting of 0 in the sleep bit puts the part into the normal mode of operation, and a setting of 1 places the part into sleep mode. sleep mode suppresses data_ready (see register 0x2e, register 0x2f, and register 0x30) , stops transmission of da ta to the fifo, and switches the sampling rate to one specified by the wake - up bits. in sleep mode, only the activity function can be used. when clearing the sleep bit, it is recommended that the part be placed into standby mode and then set back to measur ement mode with a subsequent write. this is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the sleep bit is cleared may have additional noise, especially if the device wa s asleep when the bit was cleared.
ADXL313 data sheet rev. 0 | page 20 of 28 wa k e - u p bits these bits control the frequency of readings in sleep mode as described in table 15. table 15 . frequency of readings in sleep mode setting d 1 d 0 frequency (hz) 0 0 8 0 1 4 1 0 2 1 1 1 register 0x2e int_enable (read/write) d 7 d 6 d 5 d 4 data_ready 0 0 activity d3 d2 d1 d0 inactivity 0 watermark overrun setting bits in this register to a value of 1 enables their respective functions t o generate interrupts, whereas a value of 0 prevents the functions from generating interrupts. the data_ready, watermark, and overrun bits enable only the interrupt output; the functions are always enabled. it is recommended that interrupts be configured b efore enabling their outputs. register 0x2f int_map (read/write) d 7 d 6 d 5 d 4 data_ready 0 0 activity d3 d2 d1 d0 inactivity 0 watermark overrun any bits set to 0 in this register send their respective interrupts to the int1 pin, whereas bits set to 1 s end their respective interrupts to the int 2 pin. all selected interrupts for a given pin are ored. register 0x30 int_source (read only) d 7 d 6 d 5 d 4 data_ready 0 0 activity d3 d2 d1 d0 inactivity 0 watermark overrun bits set to 1 in this register indic ate that their respective functions have triggered an event, whereas a value of 0 indicates that the corresponding event has not occurred. the data_ready, watermark, and overrun bits are always set if the corresponding events occur, regardless of the int_e nable register settings , and are cleared by reading data from the data _ x x , data _ y x , and data _ z x registers. the data_ready and watermark bits may require multiple reads, as indicated in the fifo mode descriptions in the fifo section. other bits, and the corresponding interrupts, are cleared by reading the int_source register. register 0x31 data_format (read/write) d7 d6 d5 d4 d3 d2 d1 d0 self_test spi int_invert 0 full_res justify range the data_format register co ntrols the presentation of data to register 0x32 through register 0x37. all data, except that for the 4 g range, must be clipped to avoid rollover. self_test bit a setting of 1 in the self_test bit applies a self test force to the sensor, causing a shift in the output data. a value of 0 disables the self test force. spi bit a value of 1 in the spi bit sets the device to 3 - wire spi mode, and a value of 0 sets the device to 4 - wire spi mode. int_invert bit a value of 0 in the int_invert bit sets the interru pts to active high, and a value of 1 sets the interrupts to active low. full_res bit when this bit is set to a value of 1, the device is in full resolution mode, where the output resolution increases with the g range set by the range bits to maintain 1024 lsb / g sensitivity . when the full_res bit is set to 0, the device is in 10 - bit mode, and the range bits determine the maximum g range and scale factor. justify bit a setting of 1 in the justify bit selects left (msb) justified mode, and a setting of 0 selec ts right justified (lsb) mode with sign extension. range bits these bits set the g range as described in table 16. table 16. g range setting setting d 1 d 0 range (g) 0 0 0.5 0 1 1 1 0 2 1 1 4
data sheet ADXL313 rev. 0 | page 21 of 28 register 0x32 and register 0x33 data_x0, data_x1 (read only) , register 0x34 and register 0x35 data_y0, data_y1 (read only) , register 0x36 and register 0x37 data_z0, data_z1 (read only) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data_x 0 [ 7:0] data_x1[7: 0] data_y 0[ 7:0 ] data_y 1[ 7:0 ] data_z 0[ 7:0 ] data_z 1[ 7:0 ] these six bytes (register 0x32 to register 0x37) are eight bits each and hold the output data for each axis. register 0x32 and register 0x33 hold the output data for the x - axis, register 0x34 and register 0x35 hold the output data for the y - axis, and register 0x36 and register 0x37 hold the output data for the z - axis. the output data is twos complement, with data _x0 as the least significant byte and data _ x1 as the most significant byte, where x re present x, y, or z. the data_format register (address 0x31) controls the format of the data. it is recommended that a multiple - byte read of all registers be performed to prevent a change in data between reads of sequential registers. register 0x38 fifo_ctl (read/write) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 fifo_mode trigger samples fifo_mode bits these bits set the fifo mode, as described in table 17. table 17 . fifo modes setting d 7 d 6 mode function 0 0 bypass fifo is bypassed. 0 1 fifo fifo collects up to 32 values and then stops collecting data, collecting new data only when fifo is not full. 1 0 stream fifo holds the last 32 data values. when fifo is full, the oldest data is overwritten with new er data. 1 1 trigger when triggered by the trigger bit, fifo holds the last data samples before the trigger event and then continues to collect data until full. new data is collected only when fifo is not full. trigger bit a value of 0 in the trigger bi t links the trigger event to int1, and a value of 1 links the trigger event to int 2 . samples bits the function of these bits depends on the fifo mode selected (see table 18 ). entering a value of 0 in the sample s bits immedi - ately sets the watermark status bit in the int_source register, regardless of which fifo mode is selected. undesirable opera - tion may occur if a value of 0 is used for the samples bits when trigger mode is used. table 18 . samples bits functions fifo mode samples bits function bypass none. fifo specifies how many fifo entries are needed to trigger a watermark interrupt. stream specifies how many fifo entries are needed to trigger a watermark interrupt. trigger specif ies how many fifo samples are retained in the fifo buffer before a trigger event. 0x39 fifo_status (read only) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 fifo_trig 0 entries fifo_ trig bit a 1 in the fifo_trig bit corresponds to a trigger event occurring, and a 0 means tha t a fifo trigger event has not occurred. entries bits these bits report how many data values are stored in the fifo. access to collect the data from the fifo is provided through the data _x x , data _ y x , and data _ z x registers. fifo reads must be done in burst or multiple - byte mode because each fifo level is cleared after any read (single - or multiple - byte) of the fifo. the fifo stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is ava ilable at the output filter of the device.
ADXL313 data sheet rev. 0 | page 22 of 28 applications informa tion power supply decoupl ing a 1 f tantalum capacitor (c s ) at v s and a 0.1 f ceramic capacitor (c i/o ) at v dd i/o placed close to the ADXL313 supply pins is recommended to adequately decouple the accelerometer from noise on the power supply. if additional decoupling is necessary, a resistor or ferrite bead, no larger than 100 ?, in series with v s may be helpful. additionally, i ncreasing the bypass capacitance on v s to a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor may also improve noise. ta ke c are to ensure that the connection from the ADXL313 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through v s . it is recommended that v s and v dd i/o be separate supplies to minimize digital clocking noise on the v s sup ply. if this is not possible, additional filtering of the supplies as previously mentioned may be necessary. figure 23 . application diagram mechanical considera tions for mounting mount t he ADXL313 on the pcb in a location close to a hard mounting point of the pcb to the case. mounting the ADXL313 at an unsupported pcb location, as shown in figure 24 , may result in large, apparent measurement errors due to undamped pcb vibration. placing the accelerometer near a hard mounting point ensures that any pcb vibration at the accelerometer is above the accelerometers mec hanical sensor resonant frequency and, therefore, effectively invisible to the accelerometer. multiple mounting points close to the sensor and/or a thicker pcb also help to reduce the effect of system resonance on the performance of the sensor. figure 24 . incorrectly placed accelerometers threshold the lower output data rates are achieved by decimating a common sampling frequency inside the device. the activity detection function is performed using undecimated data. because the b andwidth of the output data varies with the data rate and is lower than the bandwidth of the undecimated data, the high frequency and high g data that are used to determine activity may not be present if the output of the accelerometer is examined. this ma y result in functions triggering when accelera - tion data does not appear to meet the conditions set by the user for the corresponding function. link mode the function of the link bit in the power_ctl register (address 0x2d) is to reduce the number of activ ity interrupts that the processor must service by setting the device to look for activity only after inactivity. for proper operation of this feature, the processor must still respond to the activity and inactivity interrupts by reading the int_source reg ister (address 0x30) and, therefore, clearing the interrupts. if an activity interrupt is not cleared, the part cannot go into autosleep mode. sleep mode vs . low power mode in applications where a low data rate and low power consumption are desired (at th e expense of noise performance), it is recom - mended that low power mode be used. the use of low power mode pre serves the functionality of the data_ready interrupt and the fifo for postprocessing of the acceleration data. sleep mode, while offering a low d ata rate and low power consumption, is not intended for data acquisition. however, when sleep mode is used in conjunction with the autosleep mode and the link mode, the part can automatically switch to a low power, low sampling rate mode when inactivity is detected. to prevent the generation of redundant inactivity interrupts, the inactivity interrupt is automatically disabled and activity is enabled. when the ADXL313 is in sleep mode, the host p rocessor can also be placed into sleep mode or low power mode to save significant system power. when activity is detected, the acceler ometer automatically switches back to the original data rate of the application and provides an activity interrupt that c an be used to wake up the host processor. similar to when inactivity occurs, detection of activity events is disabled and inactivity is enabled. ADXL313 gnd int1 int2 cs scl/sclk sdo/alt address sda/sdi/sdio 3-wire or 4-wire spi or i 2 c interface v s v s c s v dd i/o v dd i/o c i/o interrupt control 1 1469-019 mounting points pcb accelerometers 1 1469-020
data sheet ADXL313 rev. 0 | page 23 of 28 using self test the self test change is defined as the difference between the acceleration output of an axis with self test enabled and the acceleration output of the same axis with self test disabled (see endnote 4 of table 1 ). this definition assumes that the sensor does not move between these two measurements because , if the sensor moves, a non self test related shift corrupts the test. proper configuration of the ADXL313 is also necessary for an accurate self test measurement. set t he part with a data rate gr eater than or equal to 100 hz. this is done by ensuring that a value greater than or equal to 0x0a is written into the rate bits (bit d3 through bit d0) in the bw_rate register (address 0x2c). the part must also be placed into normal power operation by ens uring that the low_power bit in the bw_rate register is cleared (low_power bit = 0) for accurate self test measure - ments. it is recommended that the part be set to full resolution, 4 g mode to ensure that there is sufficient dynamic range for the entire self test shift. this is done by setting bit d3 of the data_format register (address 0x31) and writing a value of 0x03 to the range bits (bit d1 and bit d0) of the dat a_format register . this results in a high dynamic range for measurement and 1024 lsb/ g se nsitivity . after the part is configured for accurate self test measurement, several samples of x - , y - , and z - axis acceleration data should be retrieved from the sensor and averaged together. the number of samples averaged is a choice of the system designer , but a recom - mended starting point is 0.1 sec worth of data, which corresponds to 10 samples at 100 hz data rate. store and label the averaged values appropriately as the self test disabled data, that is, x st_off , y st_off , and z st_off . next, enable self t est by setting bit d7 of the data_format register (address 0x31). the output needs some time (about four samples) to settle after enabling self test . after allowing the output to settle, take several samples of the x - , y - , and z - axis acceleration data , and average them . it is recommended that the same number of samples be taken for this average as was previously taken. store and label t hese averaged values appropriately as the value with self test enabled, that is, x st_on , y st_on , and z st_on . self test can then be disabled by clearing bit d7 of the data_ format register (address 0 x 31 ). with the stored values for self test enabled and disabled, the self test change is as follows: x st = x st_on ? x st_off y st = y st_on ? y st_off z st = z st_on ? z st_off because the measured output for each axis is expressed in lsbs, x st , y st , and z st are also expressed in lsbs. these values can be converted to acceleration ( g ) by multiplying each value by the sensitivity, 1024 lsb/ g , when configured for full resolution mode. when op erating in 10 - bit mode, the self test delta in lsbs varies according to the selected g range, even though the self test force, in g , remains unchanged. using a range below 4 g may result in insufficient dynamic range and should be considered when selectin g the range of operation for measuring self test . if the self test change is within the valid range, the test is considered successful. generally, a part is considered to pass if the minimum magnitude of change is achieved. however, a part that changes by more than the maximum magnitude is not necessarily a failure.
ADXL313 data sheet rev. 0 | page 24 of 28 3200 hz and 1600 hz odr data f ormatting the following section applies for 3200 hz and 1600 hz output data rates only . this section can be ignored for all other data rates. for 3200 hz and 160 0 hz output data rates, w hen the ADXL313 is configured for either a 0.5 g output range or the full resolution mode is enabled , the lsb of the output data - word is always 0. if the acceleration data - word is right justified, this corresponds to bit d0 of the data _ x0 register, as shown in figure 25 and table 19. when data is left justified and the part is opera ting in 0.5 g m ode, the lsb of the output data - word is bit d6 of the datax0 register. in full resolution operation, the location of the lsb changes according to the selected output range. table 19 and figure 26 demonstrate how the position of the lsb change s when full resolution mode is enabled. table 19 . conditions for which the lsb is set to 0 (3200 hz and 1600 hz output data rates only) justify ( 0x31[2]) full_res (0x31[3]) range ( g ) lsb bit position 0 0 or 1 0.5 d 0 0 1 1 d 0 0 1 2 d 0 0 1 4 d 0 1 0 or 1 0.5 d 6 1 1 1 d 5 1 1 2 d 4 1 1 4 d 3 the use of 3200 hz and 1600 hz output data rates for fixed 10 - bit operation in the 1 g , 2 g , and 4 g output ranges provides an lsb that is valid and that changes according to the applied accel - eration. therefore, in these modes of operation, bit d0 is not always 0 when output data is right justified , and bit d6 is not always 0 when output da ta is left justified. figure 25 . right justified data formatting: 3200 hz and 1600 hz output data rate figure 26 . left justified data formatting: 3200 hz and 1600 hz output data rate 0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 data_x1 register data_x0 register for the right justified data: when operating the ADXL313 with an output rate of either 3200hz or 1600hz, the d0 bit of the data_x0 register is always 0 under either of the following conditions: 1) full resolution mode is enabled (any g range), or 2) device range is set to 0.5 g 1 1469-021 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 data_x1 register data_x0 register full resolution mode; lsb for 1 g range = 0 full resolution mode; lsb for 4 g range = 0 full resolution mode; lsb for 2 g range = 0 full resolution and 10-bit mode: lsb for 0.5 range = 0 1 1469-022 for the left justified data: when operating the ADXL313 with an output rate of either 3200hz or 1600hz, the lsb of the acceleration data-word is always 0 under the following conditions: 1) full resolution mode is enabled (any g range), or 2) device range is set to 0.5 g. full resolution mode causes the location of the lsb to change according to the selected g range. although its location may change, its value will remain 0.
data sheet ADXL313 rev. 0 | page 25 of 28 axes of acce leration sensitivity figure 27 . axes of acceleration sensitivity (corresponding output increases when accelerated along the sensitive axis) figure 28 . output response vs. orientation to gravity a z a y a x 1 1469-023 gravity x out = +1 g y out = 0 g z out = 0 g x out = ?1 g y out = 0 g z out = 0 g top x out = 0 g y out = +1 g z out = 0 g top x out = 0 g y out = ?1 g z out = 0 g top x out = 0 g y out = 0 g z out = +1 g x out = 0 g y out = 0 g z out = ?1 g top 1 1469-024
ADXL313 data sheet rev. 0 | page 26 of 28 solder profile figure 29. recommended soldering profile table 20. recommended soldering profile 1, 2 profile feature condition sn63/pb37 pb-free average ramp rate (t l to t p ) 3c/sec maximum 3c/sec maximum preheat minimum temperature (t smin ) 100c 150c maximum temperature (t smax ) 150c 200c time (t smin to t smax ) (t s ) 60 sec to 120 sec 60 sec to 180 sec t smax to t l ramp-up rate 3c/sec 3c/sec time maintained above liquidous (t l ) liquidous temperature (t l ) 183c 217c time (t l ) 60 sec to 150 sec 60 sec to 150 sec peak temperature (t p ) 240c + 0c/?5c 260c + 0c/?5c time within 5c of actual peak temperature (t p ) 10 sec to 30 sec 20 sec to 40 sec ramp-down rate 6c/sec maximum 6c/sec maximum time 25c to peak temperature 6 min maximum 8 min maximum 1 based on jedec st andard j-std-020d.1. 2 for best results, make sure that the soldering profile is in accordance with the recommendations of the manufacturer of the so lder paste used. supplier t p t c user t p t c maximum ramp-up rate = 3c/sec maximum ramp-down rate = 6c/sec preheat area t c t c ? 5c t c ? 5c t smax t smax t l t p t p t l t s supplier t p user t p tempe r atur e time time 25c to peak 25 11469-025
data sheet ADXL313 rev. 0 | page 27 of 28 outline dimensions figure 30 . 32- lead lead frame chip scale package [lfcsp_lq] 5 m m 5 mm body, thick quad (cp - 32 - 17) dimensions shown in millimeters figure 31 . sample solder pad layout (land pattern) 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.05 0.30 0.25 0.18 5.10 5.00 sq 4.90 1.55 1.45 1.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.20 min 3.70 3.60 sq 3.50 compliant to jedec standards mo-254- ljjd . 05-29-2012-b 1 1469-027 0.30mm 0.30mm 0.30mm 0.50mm 3.60mm 5.34mm 0.57mm
ADXL313 data sheet rev. 0 | page 28 of 28 ordering guide model 1, 2 measurement range specified voltage (v) temperature range package description package option ADXL313wacpz-rl 0.5 g /1 g /2 g /4 g 3.3 ?40c to +105c 32-lead lead frame chip scale package [lfcsp_lq] cp-32-17 ADXL313wacpz-rl7 0.5 g /1 g /2 g /4 g 3.3 ?40c to +105c 32-lead lead frame chip scale package [lfcsp_lq] cp-32-17 eval-ADXL313-z evaluation board eval-ADXL313-z-s evaluation board eval-ADXL313-z-m evaluation board 1 z = rohs compliant part. 2 w = qualified for auto motive applications. automotive products the ADXL313 w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d11469-0-4/13(0)

▲Up To Search▲

Price & Availability of ADXL313

	To Download ADXL313 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .